Secure resource sharing in the context of memory controllers have been reviewed in prior approaches. The first approach discusses temporal partitioning in which a specified amount of cycles is allocated to each resource, while a second approach discusses a different type of bandwidth reservation specific to memory read requests. Another approach discusses timing channels in the context of system bus protocols. These approaches are tied to memory controller interfaces and bus protocols.
Presence of hardware Trojan in third party design IPs have been looked at by prior approaches in which HLS and concurrent error detection techniques have been used to detect and recover from the presence of malicious hardware IPs. However these approaches do not consider timing channel attacks by such IPs, nor are their designs accelerator oriented.
Certain approaches discuss providing orthogonal security using FPGAs. In these approaches, FPGAs are considered as trusted computing modules, performing secure operations after decryption and relaying the results of operation after encryption. In this usage model, a third party user cannot directly interact with FPGAs nor detect application being processed upon.
An alternate paradigm to latency insensitive design methodology includes side-channel secure cryptographic accelerators using a GALS methodology. This approach makes use of random clock frequencies for their local synchronous designs in order to obfuscate the power signatures of the design. Also in their approach the accelerator is not shared with other users. Power channel attacks for reconfigurable logic has been reviewed by prior approaches as well.